The present invention relates generally to integrated circuit devices, and in particular to the use of epitaxial silicon growth in a field-effect transistor to reduce source/drain junction leakage.
Semiconductor processors continue to strive to reduce the size of individual electrical components, thereby enabling smaller and denser integrated circuitry. One typical device is a field-effect transistor. Such typically includes opposing semiconductive source/drain regions of one conductivity type having a semiconductive channel region of opposite conductivity type therebetween. A gate construction is received over the channel region. Current can be caused to flow between the source/drain regions through the channel region by applying a suitable voltage to the gate.
The channel region is in some cases composed of background doped bulk semiconductive substrate or well material, which is also received immediately beneath the opposite type doped source/drain regions. This results in a parasitic capacitance developing between the bulk substrate/well and the source/drain regions. This can adversely affect speed and device operation, and becomes an increasingly adverse factor as device dimensions continue to decrease.
Field-effect transistors have been described having channel regions formed separately from the source/drain regions. Such separate formation can result in a grain boundary between the source/drain regions and the channel region, which can produce a junction leakage problem when the grain boundary crosses the source/drain junction.
For the reasons stated above, and for other reasons stated below that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative methods for producing field-effect transistors, and their resulting devices.
The U.S. patent application Ser. No. 09/713,844 cited above includes a method of forming a field-effect transistor (FET) including forming a channel region within a bulk semiconductive material of a semiconductor substrate. Source/drain regions are formed on opposing sides of the channel region. A dielectric region is formed within the bulk semiconductive material proximately beneath at least one of the source/drain regions. The various embodiments described herein can reduce the potential for junction leakage in a FET of the type described in U.S. patent application Ser. No. 09/713,844 by moving a grain boundary of a material interface away from the channel region of the FET. The grain boundary is moved by utilizing an epitaxial silicon growth on exposed portions of the bulk semiconductive material of the semiconductor substrate.
For one embodiment, the invention provides a method of forming a field-effect transistor. The method includes forming a channel region within a bulk semiconductor material of a semiconductor substrate, wherein the channel region comprises a monocrystalline material, exposing a portion of the monocrystalline material to a surface of the semiconductor substrate, performing an epitaxial deposition upon the exposed portion of the monocrystalline material, thereby forming extensions of monocrystalline material, and forming source/drain regions on opposing sides of the channel region, wherein the source/drain regions are in contact with the extensions of monocrystalline material.
For another embodiment, the invention provides a method of forming a field-effect transistor. The method includes forming extensions of monocrystalline material interposed between source/drain regions of the field-effect transistor and a channel region of the field-effect transistor. For a further embodiment, the method includes forming extensions of monocrystalline silicon interposed between polycrystalline silicon source/drain regions of the field-effect transistor and a monocrystalline silicon channel region of the field-effect transistor.
For yet another embodiment, the invention provides a method of forming a field-effect transistor. The method includes performing an epitaxial silicon growth subsequent to forming a channel region of the field-effect transistor and prior to forming source/drain regions of the field-effect transistor. The epitaxial silicon is grown on exposed portions of monocrystalline silicon to form the epitaxial silicon interposed between the channel region and the source/drain regions.
For still another embodiment, the invention provides a method of forming a field-effect transistor. The method includes forming a region of monocrystalline silicon to define a channel region, exposing a portion of the region of monocrystalline silicon, growing epitaxial monocrystalline silicon from the exposed portion of the region of monocrystalline silicon, and forming a region of polycrystalline silicon in contact with the epitaxial monocrystalline silicon to define a source/drain region.
For one embodiment, the invention provides a field-effect transistor (FET). The FET includes a channel region in a bulk semiconductor substrate, a first source/drain region on a first side of the channel region, a second source/drain region on a second side of the channel region, an extension of epitaxial silicon interposed between the channel region and each source/drain region, a field isolation region laterally adjoining the first source/drain region and extending beneath at least a portion of the first source/drain region, and a field isolation region laterally adjoining the second source/drain region and extending beneath at least a portion of the second source/drain region.
For another embodiment, the invention provides a FET. The FET includes a channel region in a monocrystalline silicon substrate, a first source/drain region on a first side of the channel region, a second source/drain region on a second side of the channel region, epitaxial silicon formed on the monocrystalline silicon substrate between the channel region and the source/drain regions, and a gate overlying the channel region. For a further embodiment, the source/drain regions are polycrystalline silicon.
Further embodiments of the invention include methods and apparatus of varying scope.